LTC3601_技术文档

LTC3633

Dual Channel 3A, 15V

Monolithic Synchronous

Step-Down Regulator

FeaTures

DescripTion

TheLTC^®3633isahighefficiency,dual-channelmonolithic

synchronous buck regulator using a controlled on-time,

current mode architecture, with phase lockable switching

frequency. The two channels can run 180° out of phase,

which relaxes the requirements for input and output ca-

pacitance.Theoperatingsupplyvoltagerangeisfrom3.6V

to 15V, making it suitable for dual cell lithium-ion batteries

as well as point of load power supply applications from

a 12V or 5V supply.

n

3.6V to 15V Input Voltage Range

n

3A Output Current per Channel

n

Up to 95% Efficiency

n

Low Duty Cycle Operation: 5% at 2.25MHz

n

Selectable 0°/180° Phase Shift Between Channels

n

Adjustable Switching Frequency: 500kHz to 4MHz

n

External Frequency Synchronization

n

Current Mode Operation for Excellent Line and

Load Transient Response

n

0.6V Reference Allows Low Output Voltages

Theoperatingfrequencyisprogrammableandsynchroniz-

able from 500kHz to 4MHz with an external resistor. The

high frequency capability allows the use of small surface

mount inductors and capacitors. The unique constant

frequency/controlled on-time architecture is ideal for high

step-downratioapplicationsthatoperateathighfrequency

whiledemandingfasttransientresponse.Aninternalphase

lock loop servos the on-timeofthe internalone-shottimer

to match the frequency of the internal clock or an applied

external clock.

User Selectable Burst Mode^®Operation or Forced

n

Continuous Operation

n

Output Voltage Tracking and Soft-Start Capability

n

Short-Circuit Protected

n

Overvoltage Input and Overtemperature Protection

n

Low Power 2.5V Linear Regulator Output

Power Good Status Outputs

n

Available in (4mm × 5mm) QFN-28 and 28-Lead

TSSOP Packages

The LTC3633 can select between forced continuous mode

and high efficiency Burst Mode operation.

L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks

of Linear Technology Corporation. All other trademarks are the property of their respective

owners. Protected by U.S. Patents including 5481178, 5847554, 6580258, 6304066, 6476589,

6774611.

applicaTions

n

Distributed Power Systems

Battery Powered Instruments

n

Point of Load Power Supplies

Typical applicaTion

V

IN

12V

Efficiency vs Load Current

100

90

80

70

60

50

40

30

20

10

0

100

10

47µF

x2

V

IN1

IN2

Burst Mode

OPERATION

RUN1

RUN2

INTV

CC

ITH1

ITH2

RT

2.2µF

LTC3633

MODE/SYNC

PHMODE

V2P5

TRACKSS1

PGOOD1

BOOST1

1

TRACKSS2

PGOOD2

BOOST2

0.1

0.01

0.001

0.1µF

1.5µH

1µH

V

= 5V

OUT2

5V AT 3A

OUT1

3.3V AT 3A

OUT

SW2

SW1

V

IN

= 12V

= 3.3V

V

ON2

ON1

1

10

100

1000

10000

V

FB1

FB2

LOAD CURRENT (mA)

SGND PGND

73.2k

45.3k

3633 TA01b

10k

22µF

3633 TA01a

3633fb

1

LTC3633

absoluTe MaxiMuM raTings

(Note 1)

V

, V ................................................... –0.3V to 16V

IN1 IN2

V

, V , PHMODE...................–0.3V to INTV + 0.3V

FB1 FB2 CC

IN1 IN2

, V Transient ...................................................18V

RUN1, RUN2 .................................... –0.3V to V + 0.3V

IN

PGOOD1, PGOOD2, V , V .................. –0.3V to 16V

SW1, SW2........................................ –0.3V to V + 0.3V

Operating Junction Temperature Range

(Notes 2, 3)............................................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 125°C

ON1 ON2

BOOST1, BOOST2....................................–0.3V to 19.6V

BOOST1-SW1, BOOST2-SW2.................... –0.3V to 3.6V

V2P5, INTV , TRACKSS1, TRACKSS2...... –0.3V to 3.6V

CC

ITH1, ITH2, RT, MODE/SYNC........–0.3V to INTV + 0.3V

CC

pin conFiguraTion

TOP VIEW

1

2

V

ON1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ITH1

SW1

TRACKSS1

3

V

FB1

28 27 26 25 24 23

4

V

PGOOD1

PHMODE

RUN1

IN1

PGOOD1

PHMODE

RUN1

1

2

3

4

5

6

7

8

22

21

20

19

18

17

16

15

V

IN1

5

V

IN1

6

BOOST1

MODE/SYNC

RT

INTV

CC

7

INTV

CC

MODE/SYNC

RT

29

PGND

29

PGND

V2P5

8

V2P5

RUN2

BOOST2

9

BOOST2

RUN2

SGND

V

IN2

10

11

12

13

14

V

SGND

IN2

PGOOD2

V

PGOOD2

IN2

9

10 11 12 13 14

UFD PACKAGE

SW2

V

FB2

TRACKSS2

ITH2

V

ON2

FE PACKAGE

28-LEAD PLASTIC TSSOP

28-LEAD (4mm × 5mm) PLASTIC QFN

T

= 125°C, θ = 43°C/W

JMAX

JA

T

= 125°C, θ = 25°C/W

JA

JMAX

EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

LTC3633EUFD#PBF

LTC3633IUFD#PBF

LTC3633EFE#PBF

LTC3633IFE#PBF

TAPE AND REEL

PART MARKING*

3633

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3633EUFD#TRPBF

LTC3633IUFD#TRPBF

LTC3633EFE#TRPBF

LTC3633IFE#TRPBF

–40°C to 125°C

28-Lead (4mm × 5mm) Plastic QFN

28-Lead Plastic TSSOP

3633

LTC3633FE

28-Lead Plastic TSSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3633fb

2

LTC3633

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating junction

temperature range, otherwise specifications are at T_J= 25°C (Note 2). V_IN1= V_IN2= 12V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

IN

Supply Range

3.6

15

V

I

Input DC Supply Current (V + V

)

IN2

Q

IN1

Both Channels Active (Note 4)

Sleep Current

MODE = 0V

1.3

500

13

mA

µA

MODE = INTV , V , V > 0.6

CC FB1 FB2

Shutdown

RUN1 = RUN2 = 0V

l

V

Feedback Reference Voltage

0.594

0.6

0.606

30

V

%/V

%

FB

∆V

Reference Voltage Line Regulation

Output Voltage Load Regulation

Feedback Pin Input Current

Error Amplifier Transconductance

Minimum On Time

V

= 3.6V to 15V

0.02

0.05

LINE_REG

IN

ITH = 0.8V to 1.6V

LOAD_REG

I

FB

nA

g

ITH = 1.2V

1.8

20

40

mS

ns

m(EA)

t

f

V

= 1V, V = 4V

ON

IN

Minimum Off Time

= 6V

60

ns

OFF

OSC

IN

Oscillator Frequency

= INTV

1.4

1.7

3.4

2

4

2.6

2.3

4.6

MHz

RT

CC

RT = 160k

RT = 80k

I

Valley Switch Current Limit

2.6

3.5

4.5

A

LIM

R

Top Switch On-Resistance

Bottom Switch On-Resistance

130

65

mΩ

DS(ON)

I

Switch Leakage Current

V

IN

= 15V, V = 0V

RUN

0.01

1

µA

SW(LKG)

V

Overvoltage Lockout Threshold

V

IN

V

IN

Rising

Falling

16.8

15.8

17.5

16.5

18

17

V

VIN-OV

IN

INTV Voltage

3.6V < V < 15V, 0mA Load

3.1

3.3

0.7

3.5

V

CC

IN

INTV Load Regulation

0mA to 50mA Load, V = 4V to 15V

%

CC

IN

l

RUN Threshold Rising

RUN Threshold Falling

1.18

0.98

1.22

1.01

1.26

1.04

V

RUN Leakage Current

V2P5 Voltage

V

= 15V

0

3

µA

V

IN

l

I

= 0mA to 10mA

2.46

2.5

2.54

LOAD

PGOOD Good-to-Bad Threshold

V

FB

V

FB

Rising

Falling

8

–8

10

–10

%

PGOOD Bad-to-Good Threshold

V

Rising

Falling

–3

3

–5

5

%

FB

R

PGOOD Pull-Down Resistance

Power Good Filter Time

Internal Soft-Start Time

10mA Load

15

40

Ω

µs

V

PGOOD

SS

t

20

10% to 90% Rise Time

TRACKSS = 0.3V

400

0.3

1.4

700

V

During Tracking

0.28

0.315

FB

I

TRACKSS Pull-Up Current

PHMODE Threshold Voltage

µA

TRACKSS

V

PHMODE V

1

V

PHMODE

IH

IL

0.3

0.4

V

MODE/SYNC Threshold Voltage

MODE V

V

MODE/SYNC

IH

IL

SYNC Threshold Voltage

MODE/SYNC Input Current

SYNC V

0.95

V

IH

I

MODE = 0V

MODE = INTV

1.5

–1.5

µA

MODE

CC

3633fb

3

LTC3633

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

impedance and other environmental factors. The junction temperature

(T , in °C) is calculated from the ambient temperature (T , in °C) and

J

A

power dissipation (P , in watts) according to the formula:

D

T = T + (P • θ ), where θ (in °C/W) is the package thermal

J

A

D

JA

Note 2: The LTC3633 is tested under pulsed load conditions such that

impedance.

T

≈

T . The LTC3633E is guaranteed to meet performance specifications

J

A

Note 3: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 4: Dynamic supply current is higher due to the internal gate charge

being delivered at the switching frequency.

from 0°C to 85°C junction temperature. Specifications over the

–40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LTC3633I is guaranteed over the full –40°C to 125°C operating

junction temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

3633fb

4

LTC3633

Typical perForMance characTerisTics ^T_J^{= 25°C, V}_IN= 12V, f_SW= 1MHz, L = 1µH unless

otherwise noted.

Efficiency vs Load Current

Forced Continuous Mode

Operation

Efficiency vs Load Current

Burst Mode Operation

Efficiency vs Load Current

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

= 1.8V

V

= 1.8V

Burst Mode

OPERATION

OUT

FORCED

CONTINUOUS

OPERATION

V

= 4V

= 8V

= 12V

V

= 4V

= 8V

= 12V

IN

V

OUT

V

OUT

= 5V

= 3.3V

1

10

100

1000

10000

1

10

100

1000

10000

1

10

100

1000

10000

LOAD CURRENT (mA)

3633 G01

3633 G02

3633 G03

Efficiency vs Input Voltage

Burst Mode Operation

Reference Voltage

vs Temperature

Efficiency vs Load Current

100

90

80

70

60

50

40

30

20

10

0

100

95

90

85

80

75

70

65

60

0.605

0.603

0.601

0.599

0.597

0.595

V

OUT

= 1.8V

V

= 1.2V

OUT

I

= 10mA

= 100mA

= 1A

V

= 4V

LOAD

IN

I

= 8V

LOAD

= 12V

= 15V

= 3A

0.1

1

10

100

1000 10000

4

6

8

10

12

14

16

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

LOAD CURRENT (mA)

INPUT VOLTAGE (V)

3633 G04

3633 G05

3633 G06

Oscillator Frequency

vs Temperature

Oscillator Internal Set Frequency

vs Temperature

Load Regulation

2.6

2.4

2.2

2.0

1.8

1.6

1.4

10

8

1.6

1.2

R

T

= INTV

CC

Burst Mode OPERATION

FORCED CONTINUOUS

6

4

2

0.8

0

–2

–4

–6

–8

–10

0.4

0.0

–0.4

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

0

0.5

1

1.5

2

2.5

3

TEMPERATURE (°C)

I

(A)

LOAD

3633 G09

3633 G08

3633 G07

3633fb

5

LTC3633

Typical perForMance characTerisTics ^T_J^{= 25°C, V}_IN= 12V, f_SW= 1MHz, L = 1µH unless

otherwise noted.

Internal MOSFET R_DS(ON)

vs Temperature

Quiescent Current vs V_IN

Burst Mode Operation

Shutdown Current vs V_IN

800

700

600

500

400

300

200

100

0

160

140

120

100

20

18

16

14

12

10

8

TOP SWITCH

80

60

40

20

0

BOTTOM SWITCH

6

4

T

A

T

A

T

A

= 90°C

= 25°C

= –40°C

2

0

4

6

8

10

(V)

12

14

16

–50 –25

0

25

50

75 100 125

4

6

8

10

(V)

12

14

16

V

TEMPERATURE (°C)

V

IN

3633 G11

3633 G10

3633 G12

Valley Current Limit

vs Temperature

Track Pull-Up Current

vs Temperature

Switch Leakage vs Temperature

7000

6000

5000

4000

3000

2000

1000

0

2.0

3.9

3.8

3.7

3.6

3.5

3.4

3.3

MAIN SWITCH

SYNCHRONOUS SWITCH

1.8

1.6

1.4

1.2

1.0

0.8

0.6

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

75

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

3633 G13

3633 G15

3633 G14

V2P5 Load Regulation

Burst Mode Operation

Load Step

2.506

2.504

2.502

2.500

2.498

2.496

2.494

V

OUT

SW

AC-COUPLED

100mV/DIV

10V/DIV

V

OUT

50mV/DIV

I

L

2A/DIV

I

L

1A/DIV

3633 G17

3633 G18

5µs/DIV

20µs/DIV

= 100mA to 3A

= 220pF

= 13kΩ

V

I

ITH

R

= 1.8V

V

LOAD

= 1.8V

= 100mA

OUT

LOAD

OUT

I

C

0

2

4

I

6

(mA)

8

10

ITH

LOAD

3633 G16

3633fb

6

LTC3633

Typical perForMance characTerisTics ^T_J^{= 25°C, V}_IN= 12V, f_SW= 1MHz, L = 1µH unless

otherwise noted.

Start-Up (Forced Continuous Mode)

Load Step (Internal Compensation)

Start-Up (Burst Mode Operation)

V

RUN

2V/DIV

RUN

2V/DIV

OUT

AC-COUPLED

100mV/DIV

V

OUT

1V/DIV

OUT

1V/DIV

I

L

2A/DIV

I

L

1A/DIV

L

2A/DIV

3633 G19

3633 G20

3633 G21

20µs/DIV

400µs/DIV

V

I

= 1.8V

C

I

= 4.7nF

LOAD

C

LOAD

= 4.7nF

SS

OUT

LOAD

SS

= 100mA to 3A

= 150mA

I

= 150mA

ITH = INTV

CC

Start-Up into Prebiased Output

(Forced Continuous Mode)

Start-Up into Prebiased Output

(Burst Mode Operation)

RUN

2V/DIV

RUN

2V/DIV

V

OUT

1.8V

V

OUT

1.8V

1V/DIV

I

L

1A/DIV

2A/DIV

3633 G22

200µs/DIV

1ms/DIV

I

= 0mA

I

= 0mA

LOAD

3633fb

7

LTC3633

pin FuncTions ^(QFN/TSSOP)

PGOOD1 (Pin 1/Pin 4): Channel 1 Open-Drain Power

ance once the V pin returns to within 5% (typical) of

FB2

Good Output Pin. PGOOD1 is pulled to ground when the

the internal reference.

voltage on the V pin is not within 8% (typical) of the

FB1

V

(Pin 9/Pin 12): Channel 2 Output Feedback Voltage

FB2

internal 0.6V reference. PGOOD1 becomes high imped-

Pin.Inputtotheerroramplifierthatcomparesthefeedback

voltagetotheinternal0.6Vreferencevoltage. Connectthis

pin to a resistor divider network to program the desired

output voltage.

ance once the V pin returns to within 5% (typical) of

FB1

the internal reference.

PHMODE (Pin 2/Pin 5): Phase Select Input. Tie this pin

to ground to force both channels to switch in phase. Tie

TRACKSS2(Pin10/Pin13):OutputTrackingandSoft-Start

Input Pin for Channel 2. Forcing a voltage below 0.6V on

this pin bypasses the internal reference input to the error

amplifier. The LTC3633 will servo the FB pin to the TRACK

voltageunderthiscondition.Above0.6V,thetrackingfunc-

tion stops and the internal reference resumes control of

the error amplifier. An internal 1.4µA pull up current from

this pin to INTV to force both channels to switch 180°

CC

out of phase. Do not float this pin.

RUN1 (Pin 3/Pin 6): Channel 1 Regulator Enable Pin.

Enables channel 1 operation by tying RUN1 above 1.22V.

Tying it below 1V places channel 1 into shutdown. Do not

float this pin.

INTV allows a soft start function to be implemented by

CC

MODE/SYNC (Pin 4/Pin 7): Mode Select and External

Synchronization Input. Tie this pin to ground to force

continuous synchronous operation at all output loads.

connecting a capacitor between this pin and SGND.

ITH2 (Pin 11/Pin 14): Channel 2 Error Amplifier Output

and Switching Regulator Compensation Pin. Connect this

pin to appropriate external components to compensate

the regulator loop frequency response. Connect this pin

FloatingthispinortyingittoINTV enableshighefficiency

CC

Burst Mode operation at light loads. Drive this pin with a

clock to synchronize the LTC3633 switching. An internal

phase-locked loop will force the bottom power NMOS’s

turn on signal to be synchronized with the rising edge of

the CLKIN signal. When this pin is driven with a clock,

forced continuous mode is automatically selected.

to INTV to use the default internal compensation.

CC

V

(Pin 12/Pin 15): On-Time Voltage Input for Chan-

ON2

nel 2. This pin sets the voltage trip point for the on-time

comparator. Tying this pin to the output voltage makes

RT (Pin 5/Pin 8): Oscillator Frequency Program Pin.

Connect an external resistor (between 80k to 640k) from

this pin to SGND in order to program the frequency from

500kHz to 4MHz. When RT is tied to INTV , the switching

frequency will default to 2MHz.

the on-time proportional to V

V

when V

< 6V. When

OUT2

> 6V, switching frequency may become higher than

OUT2

the set frequency. The pin impedance is nominally 140kΩ.

CC

SW2 (Pins 13, 14/Pins 16, 17): Channel 2 Switch Node

Connection to External Inductor. Voltage swing of SW is

RUN2 (Pin 6/Pin 9): Channel 2 Regulator Enable Pin.

Enables channel 2 operation by tying RUN2 above 1.22V.

Tying it below 1V places channel 2 into shutdown. Do not

float this pin.

from a diode voltage drop below ground to V .

IN

V

(Pins 15, 16/Pins 18, 19): Power Supply Input for

IN2

Channel 2. Input voltage to the on chip power MOSFETs

on channel 2. This input is capable of operating from a

different supply voltage than V

SGND (Pin 7/Pin 10): Signal Ground Pin. This pin should

have a low noise connection to reference ground. The

feedbackresistornetwork,externalcompensationnetwork,

and RT resistor should be connected to this ground.

.

IN1

BOOST2 (Pin 17/Pin 20): Boosted Floating Driver Supply

for Channel 2. The (+) terminal of the bootstrap capacitor

connects to this pin while the (–) terminal connects to

the SW pin. The normal operation voltage swing of this

PGOOD2 (Pin 8/Pin 11): Channel 2 Open-Drain Power

Good Output Pin. PGOOD2 is pulled to ground when the

pin ranges from a diode voltage drop below INTV up

CC

voltage on the V pin is not within 8% (typical) of the

to V +INTV .

IN CC

FB2

internal 0.6V reference. PGOOD2 becomes high imped-

3633fb

8

LTC3633

pin FuncTions ^(QFN/TSSOP)

V2P5 (Pin 18/Pin 21): 2.5V Regulator Output. Outputs a

regulated2.5Vsupplyvoltagecapableofsupplying10mA.

Bypass this pin with a minimum of 1µF low ESR ceramic

V

< 6V. When V

> 6V, switching frequency may

OUT1

become higher than the set frequency. The pin impedance

is nominally 140kΩ.

capacitor. Tie this pin to INTV when this output is not

CC

ITH1 (Pin 26/Pin 1): Channel 1 Error Amplifier Output and

Switching Regulator Compensation Pin. Connect this pin

to appropriate external components to compensate the

regulator loop frequency response. Connect this pin to

being used in the application.

INTV (Pin 19/Pin 22): Internal 3.3V Regulator Output.

CC

Theinternalpowerdriversandcontrolcircuitsarepowered

from this voltage. The internal regulator is disabled when

both channel 1 and channel 2 are disabled with the RUN1/

RUN2 inputs. Decouple this pin to power ground with a

minimum of 1µF low ESR ceramic capacitor.

INTV to use the default internal compensation.

CC

TRACKSS1 (Pin 27/Pin 2): Output Tracking and Soft-Start

Input Pin for Channel 1. Forcing a voltage below 0.6V on

this pin bypasses the internal reference input to the error

amplifier. The LTC3633 will servo the FB pin to the TRACK

voltage. Above 0.6V, the tracking function stops and the

internal reference resumes control of the error amplifier.

BOOST1 (Pin 20/Pin 23): Boosted Floating Driver Supply

for Channel 1. The (+) terminal of the bootstrap capacitor

connects to this pin while the (–) terminal connects to

the SW pin. The normal operation voltage swing of this

An internal 1.4µA pull up current from INTV allows a

CC

pin ranges from a diode voltage drop below INTV up

soft-start function to be implemented by connecting a

CC

to V + INTV .

capacitor between this pin and SGND.

IN

CC

V

(Pins 21,22/Pins 24, 25): Power Supply Input for

V

(Pin 28/Pin 3): Channel 1 Output Feedback Voltage

IN1

FB1

Channel 1. Input voltage to the on chip power MOSFETs

Pin.Inputtotheerroramplifierthatcomparesthefeedback

voltagetotheinternal0.6Vreferencevoltage. Connectthis

pin to a resistor divider network to program the desired

output voltage.

on channel 1. The internal LDO for INTV is powered off

of this pin.

CC

SW1 (Pins 23,24/Pins 26, 27): Channel 1 Switch Node

Connection to External Inductor. Voltage swing of SW is

PGND (Exposed Pad Pin 29/Exposed Pad Pin 29): Power

from a diode voltage drop below ground to V .

GroundPin. The(–)terminaloftheinputbypasscapacitor,

IN

C , and the (–) terminal of the output capacitor, C

,

IN

OUT

V

(Pin 25/Pin 28): On-Time Voltage Input for Chan-

ON1

should be tied to this pin with a low impedance connec-

tion. This pin must be soldered to the PCB to provide low

impedance electrical contact to power ground and good

thermal contact to the PCB.

nel 1. This pin sets the voltage trip point for the on-time

comparator. Tying this pin to the regulated output volt-

age makes the on-time proportional to V

when

OUT1

3633fb

9

LTC3633

block DiagraM

C

IN

RUN

1.22V

V

ON

V

IN

140k

A

= 1

+

RUN

–

V

INTV

CC

V

IN

0.72V

6V

RUN

I

ON

I

V

VON

ON

OSC1

R

S

t

=

ON

CONTROLLER

ON

I

ION

Q

BOOST

SW

SWITCH

LOGIC

TG

AND

M1

M2

C

BOOST

L1

ANTI-

SHOOT

THROUGH

C

OUT

BG

–

I

REV

CMP

PGND

+

–

COMP

SELECT

SENSE

+

SENSE

R2

R1

ITH

FB

R

C

IDEAL DIODES

C

0.6V

REF

C1

–

EA

0.648V

–

+

INTERNAL

SOFT-START

0V

PGOOD

INTV

CC

1.4µA

TRACKSS

TRACK

–

+

–

+

FC BURST

UV

SS

MODE

SELECT

C

SS

0.552V

0.48V AT START-UP

0.10V AFTER START-UP

CHANNEL 1

OSC1

RT

OSC

PLL-SYNC

MODE/SYNC

INTV

OSC

CC

3.3V

REG

R

RT

V

IN1

C

VCC

PHMODE

PHASE

SELECT

V2P5

2.5V

REG

OSC2

SGND

CHANNEL 2 (SAME AS CHANNEL 1)

3633 BD

3633fb

10

LTC3633

operaTion

The LTC3633 is a dual-channel, current mode monolithic the MODE/SYNC pin to ground, which forces continuous

synchronous operation regardless of output load current.

step down regulator capable of providing 3A of output

current from each channel. Its unique controlled on-time

architecture allows extremely low step-down ratios while

maintainingaconstantswitchingfrequency. Eachchannel

is enabled by raising the voltage on the RUN pin above

1.22V nominally.

“Power Good” Status Output

The PGOOD open-drain output will be pulled low if the

regulatoroutputexitsa 8%windowaroundtheregulation

point. This condition is released once regulation within a

5% window is achieved. To prevent unwanted PGOOD

Main Control Loop

glitches during transients or dynamic V

changes, the

OUT

LTC3633 PGOOD falling edge includes a filter time of ap-

proximately 40µs.

In normal operation, the internal top power MOSFET is

turned on for a fixed interval determined by a fixed one-

shot timer (“ON” signal in Block Diagram). When the top

powerMOSFETturnsoff,thebottompowerMOSFETturns

V Overvoltage Protection

IN

on until the current comparator I

trips, thus restarting

In order to protect the internal power MOSFET devices

against transient voltage spikes, the LTC3633 constantly

CMP

the one shot timer and initiating the next cycle. Inductor

current is measured by sensing the voltage drop across

the SW and PGND nodes of the bottom power MOSFET.

The voltage on the ITH pin sets the comparator threshold

corresponding to inductor valley current. The error ampli-

fier EA adjusts this ITH voltage by comparing an internal

monitors each V pin for an overvoltage condition. When

IN

V rises above 17.5V, the regulator suspends operation

IN

by shutting off both power MOSFETs on the correspond-

ing channel. Once V drops below 16.5V, the regulator

IN

immediately resumes normal operation. The regulator

0.6V reference to the feedback signal V derived from the does not execute its soft-start function when exiting an

FB

overvoltage condition.

output voltage. If the load current increases, it causes a

drop in the feedback voltage relative to the internal refer-

ence. The ITH voltage then rises until the average inductor

current matches that of the load current.

Out-Of-Phase Operation

Tying the PHMODE pin high sets the SW2 falling edge to

be 180° out of phase with the SW1 falling edge. There is

a significant advantage to running both channels out of

phase. Whenrunningthechannelsinphase, bothtop-side

MOSFETs are on simultaneously, causing large current

pulses to be drawn from the input capacitor and supply

at the same time.

The operating frequency is determined by the value of the

RT resistor, which programs the current for the internal

oscillator.Aninternalphase-lockedloopservostheswitch-

ing regulator on-time to track the internal oscillator edge

and force a constant switching frequency. A clock signal

can be applied to the MODE/SYNC pin to synchronize the

switching frequency to an external source. The regulator

defaults to forced continuous operation once the clock

signal is applied.

When running the LTC3633 channels out of phase, the

large current pulses are interleaved, effectively reducing

the amount of time the pulses overlap. Thus, the total

RMS input current is decreased, which both relaxes the

Atlightloadcurrents,theinductorcurrentcandroptozero

and become negative. In Burst Mode operation, a current

capacitance requirements for the V bypass capacitors

IN

and reduces the voltage noise on the supply line.

reversal comparator (I ) detects the negative inductor

REV

current and shuts off the bottom power MOSFET, result-

ing in discontinuous operation and increased efficiency.

Both power MOSFETs will remain off until the ITH voltage

rises above the zero current level to initiate another cycle.

One potential disadvantage to this configuration occurs

when one channel is operating at 50% duty cycle. In this

situation, switching noise can potentially couple from one

channel to the other, resulting in frequency jitter on one

During this time, the output capacitor supplies the load or both channels. This effect can be mitigated with a well

current and the part is placed into a low current sleep designed board layout.

mode. Discontinuous mode operation is disabled by tying

3633fb

11

LTC3633

applicaTions inForMaTion

resistor. This internal resistor is more sensitive to pro-

cess and temperature variations than an external resistor

(seeTypicalPerformanceCharacteristics)andisbestused

for applications where switching frequency accuracy is

not critical.

A general LTC3633 application circuit is shown on the

first page of this data sheet. External component selection

is largely driven by the load requirement and switching

frequency. Component selection typically begins with the

selectionoftheinductorLandresistorR .Oncetheinductor

T

is chosen, the input capacitor, C , and the output capaci-

IN

Inductor Selection

tor, C , can be selected. Next, the feedback resistors

OUT

are selected to set the desired output voltage. Finally, the

remaining optional external components can be selected

for functions such as external loop compensation, track/

Foragiveninputandoutputvoltage,theinductorvalueand

operatingfrequencydeterminetheinductorripplecurrent.

More specifically, the inductor ripple current decreases

with higher inductor value or higher operating frequency

according to the following equation:

soft-start, V UVLO, and PGOOD.

IN

Programming Switching Frequency





















V_OUT

f •L

V

^OUT

IN

Selectionoftheswitchingfrequencyisatrade-offbetween

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

Operation at lower frequencies improves efficiency by

reducing internal gate charge losses but requires larger

inductance values and/or capacitance to maintain low

output ripple voltage.

ΔI =

1–

L



Where∆I =inductorripplecurrent,f=operatingfrequency

L

and L = inductor value. A trade-off between component

size, efficiency and operating frequency can be seen from

this equation. Accepting larger values of ∆I allows the

L

useoflowervalueinductorsbutresultsingreaterinductor

core loss, greater ESR loss in the output capacitor, and

larger output voltage ripple. Generally, highest efficiency

operation is obtained at low operating frequency with

small ripple current.

Connecting a resistor from the RT pin to SGND programs

the switching frequency (f) between 500kHz and 4MHz

according to the following formula:

3.2E¹¹

R_RT=

f

A reasonable starting point is to choose a ripple current

that is about 40% of I

. Note that the largest

OUT(MAX)

where R is in Ω and f is in Hz.

RT

ripple current occurs at the highest V . Exceeding 60%

IN

When RT is tied to INTV , the switching frequency will

CC

of I

is not recommended. To guarantee that

OUT(MAX)

default to approximately 2MHz, as set by an internal

ripple current does not exceed a specified maximum, the

inductance should be chosen according to:

6000















V_OUT

f • ΔI_L(MAX)

V_OUT



5000

4000

3000

2000

1000

L =

1–

_IN(MAX)

V



Once the value for L is known, the type of inductor must

be selected. Actual core loss is independent of core size

for a fixed inductor value, but is very dependent on the

inductance selected. As the inductance increases, core

losses decrease. Unfortunately, increased inductance

requires more turns of wire, leading to increased DCR

and copper loss.

0

100 200 300 400 500 600 700

R RESISTOR (kΩ)

T

3633 F01

Figure 1. Switching Frequency vs R_T

3633fb

12

LTC3633

applicaTions inForMaTion

Ferrite designs exhibit very low core loss and are pre-

ferred at high switching frequencies, so design goals

can concentrate on copper loss and preventing satura-

tion. Ferrite core material saturates “hard”, which means

that inductance collapses abruptly when the peak design

current is exceeded. This results in an abrupt increase in

inductor ripple current, so it is important to ensure that

the core will not saturate.

C and C

Selection

OUT

IN

The input capacitance, C , is needed to filter the trapezoi-

IN

dal wave current at the drain of the top power MOSFET.

To prevent large voltage transients from occurring, a low

ESR input capacitor sized for the maximum RMS current

is recommended. The maximum RMS current is given by:

V_OUTV − V

(

)

IN

OUT

I_RMS=I_OUT(MAX)

Different core materials and shapes will change the size/

currentandprice/currentrelationshipofaninductor.Toroid

or shielded pot cores in ferrite or permalloy materials are

small and don’t radiate much energy, but generally cost

more than powdered iron core inductors with similar

characteristics. The choice of which style inductor to use

mainly depends on the price versus size requirements

and any radiated field/EMI requirements. Table 1 gives a

sampling of available surface mount inductors.

V

IN

This formula has a maximum at V = 2V , where

IN

OUT

I

≅ I /2. This simple worst case condition is com-

RMS

OUT

monlyusedfordesignbecauseevensignificantdeviations

do not offer much relief. Note that ripple current ratings

from capacitor manufacturers are often based on only

2000 hours of life which makes it advisable to further de-

rate the capacitor, or choose a capacitor rated at a higher

temperature than required.

Table 1. Inductor Selection Table

MAX

Several capacitors may also be paralleled to meet size or

height requirements in the design. For low input voltage

applications, sufficient bulk input capacitance is needed

to minimize transient effects during output load changes.

Even though the LTC3633 design includes an overvoltage

protection circuit, care must always be taken to ensure

inputvoltagetransientsdonotposeanovervoltagehazard

to the part.

INDUCTANCE DCR

(µH) (mΩ)

CURRENT

(A)

DIMENSIONS

(mm)

HEIGHT

(mm)

Würth Electronik WE-HC 744312 Series

0.25

0.47

0.72

1.0

2.5

3.4

18

16

12

11

9

3.8

7 × 7.7

7.5

9.5

10.5

1.5

Vishay IHLP-2020BZ-01 Series

The selection of C

is determined by the effective series

OUT

0.22

0.33

0.47

0.68

1

5.2

8.2

8.8

12.4

20

15

12

2

5.2 × 5.5

resistance(ESR)thatisrequiredtominimizevoltageripple

and load step transients as well as the amount of bulk

capacitance that is necessary to ensure that the control

loop is stable. Loop stability can be checked by viewing

11.5

10

7

Toko FDV0620 Series

the load transient response. The output ripple, ∆V , is

0.20

0.47

1.0

4.5

8.3

18.3

12.4

9.0

5.7

2.0

5.0

3.2

7 × 7.7

6 × 8.9

OUT

approximated by:







Coilcraft D01813H Series

1

∆V_OUT< ∆I ESR+

_L

0.33

0.56

1.2

4

10

17

10

7.7

5.3

8 • f • C



_OUT

When using low-ESR ceramic capacitors, it is more useful

tochoosetheoutputcapacitorvaluetofulfillachargestor-

age requirement. During a load step, the output capacitor

TDK RLF7030 Series

1.0

1.5

8.8

9.6

6.4

6.1

6.9 × 7.3

3633fb

13

LTC3633

applicaTions inForMaTion

mustinstantaneouslysupplythecurrenttosupporttheload

until the feedback loop raises the switch current enough

to support the load. The time required for the feedback

looptorespondisdependentonthecompensationandthe

output capacitor size. Typically, 3 to 4 cycles are required

to respond to a load step, but only in the first cycle does

INTV Regulator Bypass Capacitor

CC

An internal low dropout (LDO) regulator produces the

3.3V supply that powers the internal bias circuitry and

drives the gate of the internal MOSFET switches. The

INTV pin connects to the output of this regulator and

CC

must have a minimum of 1µF ceramic decoupling capaci-

the output drop linearly. The output droop, V

, is

DROOP

tance to ground. The decoupling capacitor should have

usually about 3 times the linear drop of the first cycle.

Thus, a good place to start is with the output capacitor

size of approximately:

low impedance electrical connections to the INTV and

CC

PGND pins to provide the transient currents required by

the LTC3633. This supply is intended only to supply ad-

ditional DC load currents as desired and not intended to

regulate largetransientorACbehavior, asthismayimpact

LTC3633 operation.

3• ∆I_OUT

f • V_DROOP

C_OUT

≈

Thoughthisequationprovidesagoodapproximation,more

capacitance may be required depending on the duty cycle

Boost Capacitor

and load step requirements. The actual V

should be

The LTC3633 uses a “bootstrap” circuit to create a voltage

DROOP

verified by applying a load step to the output.

railabovetheappliedinputvoltageV .Specifically,aboost

IN

capacitor, C

, is charged to a voltage approximately

BOOST

Using Ceramic Input and Output Capacitors

equal to INTV each time the bottom power MOSFET is

CC

turned on. The charge on this capacitor is then used to

supplytherequiredtransientcurrentduringtheremainder

oftheswitchingcycle. WhenthetopMOSFETisturnedon,

Higher values, lower cost ceramic capacitors are available

in small case sizes. Their high ripple current, high voltage

ratingandlowESRmakethemidealforswitchingregulator

applications. However, due to the self-resonant and high-

Q characteristics of some types of ceramic capacitors,

care must be taken when these capacitors are used at

the input. When a ceramic capacitor is used at the input

and the power is supplied by a wall adapter through long

wires, a load step at the output can induce ringing at the

the BOOST pin voltage will be equal to approximately V

IN

+ 3.3V. For most applications, a 0.1µF ceramic capacitor

closely connected between the BOOST and SW pins will

provide adequate performance.

Low Power 2.5V Linear Regulator

V input. Atbest, thisringingcancoupletotheoutputand

The V2P5 pin can be used as a low power 2.5V regulated

rail. This pin is the output of a 10mA linear regulator

IN

be mistaken as loop instability. At worst, a sudden inrush

of current through the long wires can potentially cause a

powered from the INTV pin. Note that the power from

CC

voltage spike at V large enough to damage the part. For

V2P5 eventually comes from V since the INTV power

IN

IN1

CC

a more detailed discussion, refer to Application Note 88.

is supplied from V . When using this output, this pin

IN1

must be bypassed with a 1µF ceramic capacitor. If this

When choosing the input and output ceramic capacitors,

choose the X5R and X7R dielectric formulations. These

dielectrics have the best temperature and voltage char-

acteristics of all the ceramics for a given value and size.

output is not being used, it is recommended to short this

output to INTV to disable the regulator.

CC

3633fb

14

LTC3633

applicaTions inForMaTion

Output Voltage Programming

will drop out of regulation. The minimum input voltage to

avoid this dropout condition is:

Each regulator’s output voltage is set by an external resis-

tive divider according to the following equation:

V_OUT

V

=

IN(MIN)

1− f•t





(

)

OFF(MIN)

R2

R1

V_OUT= 0.6V 1+









Conversely, the minimum on-time is the smallest dura-

tion of time in which the top power MOSFET can be in

its “on” state. This time is typically 20ns. In continuous

mode operation, the minimum on-time limit imposes a

minimum duty cycle of:

The desired output voltage is set by appropriate selection

of resistors R1 and R2 as shown in Figure 2. Choosing

large values for R1 and R2 will result in improved zero-

load efficiency but may lead to undesirable noise coupling

or phase margin reduction due to stray capacitances

DC_(MIN)= f•t

(

)

ON(MIN)

at the V node. Care should be taken to route the V

FB

trace away from any noise source, such as the SW trace.

where t

is the minimum on-time. As the equation

ON(MIN)

To improve the frequency response of the main control

shows, reducing the operating frequency will alleviate the

minimum duty cycle constraint.

loop, a feedforward capacitor, C , may be used as shown

F

in Figure 2.

In the rare cases where the minimum duty cycle is

surpassed, the output voltage will still remain in regula-

tion, but the switching frequency will decrease from its

programmed value. This constraint may not be of critical

importance in most cases, so high switching frequencies

may be used in the design without any fear of severe

consequences. As the sections on Inductor and Capacitor

selection show, high switching frequencies allow the use

of smaller board components, thus reducing the footprint

of the application circuit.

V

OUT

R2

C

F

FB

LTC3633

SGND

R1

3633 F02

Figure 2. Setting the Output Voltage

Minimum Off-Time/On-Time Considerations

The minimum off-time is the smallest amount of time that

the LTC3633 can turn on the bottom power MOSFET, trip

the current comparator and turn the power MOSFET back

off. This time is typically 40ns. For the controlled on-time

control architecture, the minimum off-time limit imposes

a maximum duty cycle of:

Internal/External Loop Compensation

The LTC3633 provides the option to use a fixed internal

loop compensation network to reduce both the required

external component count and design time. The internal

loop compensation network can be selected by connect-

DC_(MAX)=1– f•t

ing the ITH pin to the INTV pin. To ensure stability it is

(

)

CC

OFF(MIN)

recommendedthatinternalcompensationonlybeusedwith

applications with f > 1MHz. Alternatively, the user may

where f is the switching frequency and t

is the

SW

OFF(MIN)

choose specific external loop compensation components

to optimize the main control loop transient response as

desired. External loop compensation is chosen by simply

connecting the desired network to the ITH pin.

minimumoff-time.Ifthemaximumdutycycleissurpassed,

due to a dropping input voltage for example, the output

3633fb

15

LTC3633

applicaTions inForMaTion

Suggestedcompensationcomponentvaluesareshownin

Figure 3. For a 2MHz application, an R-C network of 220pF

and 13kΩ provides a good starting point. The bandwidth

of the loop increases with decreasing C. If R is increased

by the same factor that C is decreased, the zero frequency

will be kept the same, thereby keeping the phase the same

in the most critical frequency range of the feedback loop.

A 10pF bypass capacitor on the ITH pin is recommended

for the purposes of filtering out high frequency coupling

from stray board capacitance. In addition, a feedforward

transient response once the final PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because their various types and values determine the

loop gain and phase. An output current pulse of 20% to

100% of full load current having a rise time of ~1µs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop.

Switching regulators take several cycles to respond to a

capacitor C can be added to improve the high frequency

F

step in load current. When a load step occurs, V

im-

OUT

•ESR,where

response, as previously shown in Figure 2. Capacitor C

F

mediatelyshiftsbyanamountequalto∆I

LOAD

provides phase lead by creating a high frequency zero

ESR is the effective series resistance of C . ∆I

also

OUT

LOAD

with R2 which improves the phase margin.

begins to charge or discharge C

generating a feedback

OUT

error signal used by the regulator to return V

to its

can

OUT

ITH

steady-state value. During this recovery time, V

OUT

R

COMP

13k

be monitored for overshoot or ringing that would indicate

a stability problem.

LTC3633

C

COMP

220pF

SGND

3633 F03

When observing the response of V

to a load step, the

OUT

initialoutputvoltagestepmaynotbewithinthebandwidthof

thefeedbackloop,sothestandardsecondorderovershoot/

DC ratio cannot be used to determine phase margin. The

output voltage settling behavior is related to the stability

of the closed-loop system and will demonstrate the actual

overall supply performance. For a detailed explanation of

optimizing the compensation components, including a

review of control loop theory, refer to Linear Technology

Application Note 76.

Figure 3. Compensation Component

Checking Transient Response

The regulator loop response can be checked by observing

theresponseofthesystemtoaloadstep.Whenconfigured

for external compensation, the availability of the ITH pin

not only allows optimization of the control loop behavior

butalsoprovidesaDC-coupledandACfilteredclosedloop

response test point. The DC step, rise time, and settling

behavioratthistestpointreflecttheclosedloopresponse.

Assuming a predominantly second order system, phase

margin and/or damping factor can be estimated using the

percentage of overshoot seen at this pin.

Insomeapplications,amoreseveretransientcanbecaused

by switching in loads with large (>10µF) input capacitors.

Thedischargedinputcapacitorsareeffectivelyputinparal-

lel with C , causing a rapid drop in V . No regulator

OUT

can deliver enough current to prevent this problem, if

the switch connecting the load has low resistance and is

driven quickly. The solution is to limit the turn-on speed

of the load switch driver. A hot swap controller is designed

specifically for this purpose and usually incorporates cur-

rent limiting, short-circuit protection, and soft starting.

The ITH external components shown in Figure 3 circuit

will provide an adequate starting point for most applica-

tions. The series R-C filter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

3633fb

16

LTC3633

applicaTions inForMaTion

MODE/SYNC Operation

The voltage at the TRACKSS pin may be driven from an

external source, or alternatively, the user may leverage

the internal 1.4µA pull-up current source to implement

a soft-start function by connecting an external capacitor

The MODE/SYNC pin is a multipurpose pin allowing both

mode selection and operating frequency synchroniza-

tion. Floating this pin or connecting it to INTV enables

CC

(C ) from the TRACKSS pin to ground. The relationship

SS

Burst Mode operation for superior efficiency at low load

currents at the expense of slightly higher output voltage

ripple. When the MODE/SYNC pin is tied to ground, forced

continuousmodeoperationisselected,creatingthelowest

fixed output ripple at the expense of light load efficiency.

between output rise time and TRACKSS capacitance is

given by:

t

= 430000Ω • C

SS

A default internal soft-start ramp forces a minimum soft-

start time of 400µs by overriding the TRACKSS pin input

during this time period. Hence, capacitance values less

than approximately 1000pF will not significantly affect

soft-start behavior.

The LTC3633 will detect the presence of the external clock

signal on the MODE/SYNC pin and synchronize the inter-

nal oscillator to the phase and frequency of the incoming

clock. The presence of an external clock will place both

regulators into forced continuous mode operation.

WhendrivingtheTRACKSSpinfromanothersource, each

channel’s output can be set up to either coincidentally or

ratiometrically track another supply’s output, as shown in

Output Voltage Tracking and Soft-Start

The LTC3633 allows the user to control the output voltage

rampratebymeansoftheTRACKSSpin.From0to0.6V,the

TRACKSS voltage will override the internal 0.6V reference

input to the error amplifier, thus regulating the feedback

voltage to that of the TRACKSS pin. When TRACKSS is

above 0.6V, tracking is disabled and the feedback voltage

will regulate to the internal reference voltage.

Figure 4. In the following discussions, V

refers to the

OUT2

OUT1

LTC3633 output 1 as a master channel and V

refers

to output 2 as a slave channel. In practice, either channel

can be used as the master.

To implement the coincident tracking in Figure 4a, con-

nect an additional resistive divider to V

and connect

OUT1

its midpoint to the TRACKSS pin of the slave channel.

V

OUT1

V

OUT2

3633 F04b

TIME

3633 F04a

(4a) Coincident Tracking

(4b) Ratiometric Tracking

Figure 4. Two Different Modes of Output Voltage Tracking

3633fb

17

LTC3633

applicaTions inForMaTion

The ratio of this divider should be the same as that of the

with 15Ω output resistance to ground, thus dropping the

PGOODpinvoltage. ThisbehaviorisdescribedinFigure6.

slave channel’s feedback divider shown in Figure 5a. In

this tracking mode, V

must be set higher than V

.

OUT2

OUT1

To implement the ratiometric tracking, the feedback pin of

the master channel should connect to the TRACKSS pin of

the slave channel (as in Figure 5b). By selecting different

resistors, the LTC3633 can achieve different modes of

tracking including the two in Figure 4.

NOMINAL OUTPUT

PGOOD

VOLTAGE

Uponstart-up,theregulatordefaultstoBurstModeopera-

–8% –5%

0%

5%

8%

OUTPUT VOLTAGE

tion until the output exceeds 80% of its final value (V

>

FB

3633 F06

0.48V).Oncetheoutputreachesthisvoltage,theoperating

mode of the regulator switches to the mode selected by

the MODE/SYNC pin as described above. During normal

operation, if the output drops below 10% of its final value

(asitmaywhentrackingdown, forinstance), theregulator

willautomaticallyswitchtoBurstModeoperationtoprevent

inductor saturation and improve TRACKSS pin accuracy.

Figure 6. PGOOD Pin Behavior

A filter time of 40µs (typical) acts to prevent unwanted

PGOOD output changes during V

transient events.

OUT

As a result, the output voltage must be within the target

regulation window of 5% for 40µs before the PGOOD pin

pulls high. Conversely, the output voltage must exit the

8% regulation window for 40µs before the PGOOD pin

pulls to ground.

Output Power Good

The PGOOD output of the LTC3633 is driven by a 15Ω

(typical) open-drain pull-down device. This device will be

turned off once the output voltage is within 5% (typical) of

the target regulation point, allowing the voltage at PGOOD

to rise via an external pull-up resistor. If the output voltage

exits an 8% (typical) regulation window around the target

regulation point, the open-drain output will pull down

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

V

OUT1

V

OUT2

OUT1

OUT2

R3

R4

R1

R2

R3

R4

R1

R2

R3

R4

TO

TRACKSS2

TO

TRACKSS2

TO

FB1

TO

FB2

TO

FB2

TO

V

FB1

3633 F05

(5a) Coincident Tracking Setup

(5b) Ratiometric Tracking Setup

Figure 5. Setup for Coincident and Ratiometric Tracking

3633fb

18

LTC3633

applicaTions inForMaTion

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

To calculate the total power loss from the LDO load,

simply add the gate charge current and quiescent cur-

rent and multiply by V :

IN

% Efficiency = 100% – (L1 + L2 + L3 +…)

P

LDO

= (I + I ) • V

GATECHG Q IN

where L1, L2, etc. are the individual losses as a percent-

age of input power.

3. Other “hidden” losses such as transition loss, copper

traceresistances,andinternalloadcurrentscanaccount

foradditionalefficiencydegradationsintheoverallpower

system. Transition loss arises from the brief amount of

time the top power MOSFET spends in the saturated

region during switch node transitions. The LTC3633

internalpowerdevicesswitchquicklyenoughthatthese

losses are not significant compared to other sources.

Although all dissipative elements in the circuit produce

losses, three main sources usually account for most of

2

the losses in LTC3633 circuits: 1) I R losses, 2) switching

losses and quiescent power loss 3) transition losses and

other losses.

2

1. I R losses are calculated from the DC resistances of

Other losses, including diode conduction losses during

dead-time and inductor core losses, generally account

for less than 2% total additional loss.

the internal switches, R , and external inductor, R .

SW

L

In continuous mode, the average output current flows

through inductor L but is “chopped” between the

internal top and bottom power MOSFETs. Thus, the

series resistance looking into the SW pin is a function

Thermal Considerations

The LTC3633 requires the exposed package backplane

metal (PGND) to be well soldered to the PC board to

provide good thermal contact. This gives the QFN and

TSSOP packages exceptional thermal properties, which

are necessary to prevent excessive self-heating of the part

in normal operation.

of both top and bottom MOSFET R

cycle (DC) as follows:

and the duty

DS(ON)

R

SW

= (R )(DC) + (R )(1 – DC)

DS(ON)TOP DS(ON)BOT

TheR

forboththetopandbottomMOSFETscanbe

DS(ON)

obtained from the Typical Performance Characteristics

2

curves. Thus to obtain I R losses:

In a majority of applications, the LTC3633 does not dis-

sipatemuchheatduetoitshighefficiencyandlowthermal

resistance of its exposed-back QFN package. However, in

applications where the LTC3633 is running at high ambi-

2

I R losses = I

(R + R )

SW L

OUT

2. The internal LDO supplies the power to the INTV rail.

CC

The total power loss here is the sum of the switching

losses and quiescent current losses from the control

circuitry.

ent temperature, high V , high switching frequency, and

IN

maximum output current load, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 150°C,

both power switches will be turned off until temperature

returns to 140°C.

Each time a power MOSFET gate is switched from low

to high to low again, a packet of charge dQ moves from

V

to ground. The resulting dQ/dt is a current out of

IN

INTV that is typically much larger than the DC control

CC

To prevent the LTC3633 from exceeding the maximum

junction temperature of 125°C, the user will need to do

some thermal analysis. The goal of the thermal analysis

biascurrent.Incontinuousmode,I

where Q and Q are the gate charges of the internal

=f(Q +Q ),

GATECHG

T B

T

B

top and bottom power MOSFETs and f is the switching

frequency. For estimation purposes, (Q + Q ) on each

T

B

LTC3633 regulator channel is approximately 2.3nC.

3633fb

19

LTC3633

applicaTions inForMaTion

is to determine whether the power dissipated exceeds the

maximum junction temperature of the part. The tempera-

ture rise is given by:

junction temperature of 109°C. If the application calls for

ahigherambienttemperatureand/orhigherloadcurrents,

care should be taken to reduce the temperature rise of the

part by using a heat sink or air flow.

T

RISE

= P • θ

D JA

Figure 7 is a temperature derating curve based on the

DC1347 demo board (QFN package). It can be used to

estimate the maximum allowable ambient temperature

for given DC load currents in order to avoid exceeding

the maximum operating junction temperature of 125°C.

As an example, consider the case when one of the regula-

tors is used in an application where V = 12V, I = 2A,

IN

OUT

frequency = 2MHz, V

= 1.8V. From the R

graphs

OUT

DS(ON)

intheTypicalPerformanceCharacteristicssection,thetop

switch on-resistance is nominally 140mΩ and the bottom

switch on-resistance is nominally 80mΩ at 70°C ambient.

3.5

3.0

2.5

2.0

1.5

The equivalent power MOSFET resistance R is:

SW

1.8V

12V

10.2V

12V

R_DS(ON)TOP

•

+R_DS(ON)BOT

•

=89mΩ

From the previous section’s discussion on gate drive, we

estimate the total gate drive current through the LDO to be

1.0

2MHz • 2.3nC = 4.6mA, and I of one channel is 0.65mA

CH2 LOAD = 0A

Q

CH2 LOAD = 1A

0.5

(see Electrical Characteristics). Therefore, the total power

CH2 LOAD = 2A

CH2 LOAD = 3A

0

dissipated by a single regulator is:

0

25

50

75

100

125

2

MAXIMUM ALLOWABLE AMBIENT

P = I

D

• R + V • (I

+ I )

GATECHG Q

OUT

SW

IN

TEMPERATURE (°C)

3633 F07

2

P = (2A) • (0.089Ω) + (12V) • (4.6mA + 0.65mA)

D

Figure 7. Temperature Derating Curve for DC1347 Demo Circuit

= 0.419W

Junction Temperature Measurement

Running two regulators under the same conditions would

result in a power dissipation of 0.838W. The QFN 5mm

× 4mm package junction-to-ambient thermal resistance,

The junction-to-ambient thermal resistance will vary de-

pending on the size and amount of heat sinking copper

on the PCB board where the part is mounted, as well as

the amount of air flow on the device. In order to properly

evaluate this thermal resistance, the junction temperature

needs to be measured. A clever way to measure the junc-

tion temperature directly is to use the internal junction

diode on one of the pins (PGOOD) to measure its diode

voltage change based on ambient temperature change.

θ ,isaround43°C/W.Therefore,thejunctiontemperature

JA

of the regulator operating in a 70°C ambient temperature

is approximately:

T = 0.838W • 43°C/W + 70°C = 106°C

J

which is below the maximum junction temperature of

125°C. With higher ambient temperatures, a heat sink or

cooling fan should be considered to drop the junction-

to-ambient thermal resistance. Alternatively, the TSSOP

packagemaybeabetterchoiceforhighpowerapplications,

sinceithasbetterthermalpropertiesthantheQFNpackage.

First remove any external passive component on the

PGOOD pin, then pull out 100μA from the PGOOD pin to

turn on its internal junction diode and bias the PGOOD

pin to a negative voltage. With no output current load,

measure the PGOOD voltage at an ambient temperature

of 25°C, 75°C and 125°C to establish a slope relationship

between the delta voltage on PGOOD and delta ambient

temperature. Once this slope is established, then the

junction temperature rise can be measured as a function

Remembering that the above junction temperature is

obtained from an R

at 70°C, we might recalculate

DS(ON)

the junction temperature based on a higher R

since

DS(ON)

it increases with temperature. Redoing the calculation

assuming that R increased 12% at 106°C yields a new

SW

3633fb

20

LTC3633

applicaTions inForMaTion

of power loss in the package with corresponding output 6) Flood all unused areas on all layers with copper in order

loadcurrent. Althoughmakingthismeasurementwiththis

method does violate absolute maximum voltage ratings

on the PGOOD pin, the applied power is so low that there

should be no significant risk of damaging the device.

to reduce the temperature rise of power components.

Thesecopperareasshouldbeconnectedtotheexposed

backside of the package (PGND).

Refer to Figures 9 and 10 for board layout examples.

Board Layout Considerations

Design Example

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3633. Check the following in your layout:

As a design example, consider using the LTC3633 in an

application with the following specifications: V

=

IN(MAX)

13.2V,V

=1.8V,V

=3.3V,I

DROOP

=3A,I

OUT1

OUT2

OUT(MAX) OUT(MIN)

1) Do the input capacitors connect to the V and PGND = 10mA, f = 2MHz, V

~ (5% • V ). The following

IN

OUT

pins as close as possible? These capacitors provide discussion will use equations from the previous sections.

the AC current to the internal power MOSFETs and their

drivers.

Because efficiency is important at both high and low load

current, Burst Mode operation will be utilized.

2) The output capacitor, C , and inductor L should be

OUT

First, the correct R resistor value for 2MHz switching fre-

T

closely connected to minimize loss. The (–) plate of

quency must be chosen. Based on the equation discussed

C

should be closely connected to both PGND and

OUT

earlier, R should be 160k; the closest standard value is

T

the (–) plate of C .

IN

162k. RT can be tied to INTV if switching frequency

CC

3) The resistive divider, (e.g. R1 to R4 in Figure 8) must be accuracy is not critical.

connected between the (+) plate of C and a ground

OUT

Next, determine the channel 1 inductor value for about

40% ripple current at maximum V :

line terminated near SGND. The feedback signal V

FB

IN

should be routed away from noisy components and







1.8V

2MHz •1.2A

1.8V

13.2V

traces, such as the SW line, and its trace length should

L1=

1−

=0.64µH







be minimized. In addition, the R resistor and loop







T

compensation components should be terminated to

Astandardvalueof0.68µHshouldworkwellhere. Solving

the same equation for channel 2 results in a 1µH inductor.

SGND.

4) Keep sensitive components away from the SW pin. The

C

will be selected based on the charge storage require-

R resistor,thecompensationcomponents,thefeedback

OUT

ment. For a V

T

of 90mV for a 3A load step:

resistors, and the INTV bypass capacitor should all

DROOP

CC

be routed away from the SW trace and the inductor L.

3• ∆I_OUT

f₀V_DROOP(2MHz)(90mV)

3•(3A)

C_OUT1

≈

=

=50µF

5) A ground plane is preferred, but if not available, the

signal and power grounds should be segregated with

bothconnectingtoacommon,lownoisereferencepoint.

The connection to the PGND pin should be made with

a minimal resistance trace from the reference point.

3633fb

21

LTC3633

applicaTions inForMaTion

A 47µF ceramic capacitor should be sufficient for channel

1. Solving the same equation for channel 2 (using 5% of

Lastly, the feedback resistors must be chosen. Picking

R1 and R3 to be 12.1k, R2 and R4 are calculated to be:

V

for V

) results in 27µF of capacitance (22µF is

OUT

DROOP





1.8V

0.6V

the closest standard value).

R2 = (12.1k) •

–1 = 24.2k









C should be sized for a maximum current rating of:

IN







3.3V

0.6V

1.8V 13.2V−1.8V

R4 = (12.1k) •

–1 = 54.5k

(

)







I_RMS= 3A

=1A

13.2V

The final circuit is shown in Figure 8.

Solving this equation for channel 2 results in an RMS

input current of 1.3A. Decoupling each V input with

IN

a 47µF ceramic capacitor should be adequate for most

applications.

V

IN

12V

C

47µF

×2

V

IN1

IN

IN2

RUN1

RUN2

INTV

CC

C2

2.2µF

ITH1

ITH2

V2P5

LTC3633

MODE/SYNC

PHMODE

TRACKSS1

PGOOD1

RT

TRACKSS2

PGOOD2

BOOST2

R5

162k

BOOST1

L2

1µH

L1

0.68µH

0.1µF

V

OUT1

OUT2

SW2

SW1

3.3V AT 3A

1.8V AT 3A

V

ON1

ON2

FB2

V

FB1

SGND PGND

R4

54.9k

R2

24.3k

R3

12.1k

R1

12.1k

C

OUT1

47µF

OUT2

22µF

3633 F08

Figure 8. Design Example Circuit

3633fb

22

LTC3633

applicaTions inForMaTion

VIA TO BOOST1

VIA TO V /R2 (NOT SHOWN)

ON1

V

OUT1

C

OUT1

L1

GND

VIAS TO GROUND

PLANE

SW1

C

IN

C

BOOST1

VIAS TO GROUND

PLANE

V

IN

SGND (TO NONPOWER

COMPONENTS)

BOOST2

IN

SW2

GND

VIAS TO GROUND

PLANE

L2

C

OUT2

V

OUT2

3633 F09

VIA TO BOOST2

VIA TO V /R4 (NOT SHOWN)

ON2

Figure 9. Example of Power Component Layout for QFN Package

VIA TO V

AND R2 (NOT SHOWN)

ON1

C

OUT1

V

OUT1

VIAS TO GROUND

PLANE

GND

VIAS TO GROUND

PLANE

L1

C

IN

VIA TO BOOST1

SW1

C

BOOST1

BOOST2

V

IN

SGND (TO NONPOWER

COMPONENTS)

SW2

L2

VIA TO BOOST2

IN

GND

VIAS TO GROUND

PLANE

V

OUT2

C

OUT2

3633 F10

VIA TO V

AND R4 (NOT SHOWN)

ON2

Figure 10. Example of Power Component Layout for TSSOP Package

3633fb

23

LTC3633

Typical applicaTions

1.2V/2.5V 4MHz Buck Regulator

V

IN

3.6V TO 15V

C1

22µF

×2

V

IN1

IN2

RUN1

RUN2

ITH2

INTV

CC

V2P5

C2

2.2µF

PHMODE

ITH1

6.98k

220pF

10pF

6.98k

220pF

10pF

LTC3633

RT

R5

80.6k

MODE/SYNC

BOOST1

BOOST2

SW2

L2

0.82µH

L1

0.47µH

0.1µF

V

OUT1

1.2V AT 3A

OUT2

2.5V AT 3A

SW1

V

ON1

ON2

FB2

V

FB1

SGND PGND

R4

31.6k

R2

10k

R3

10k

R1

10k

C

OUT1

47µF

OUT2

22µF

3633 TA02

3.3V/1.8V Sequenced Regulator with 6V Input UVLO (V_OUT1Enabled After V_OUT2

)

V

IN

6V TO 15V

R6

100k

R7

154k

C1

47µF

×2

V

IN1

IN2

RUN1

INTV

CC

C2

2.2µF

PGOOD2

RUN2

ITH1

ITH2

V2P5

LTC3633

R8

40k

MODE/SYNC

PHMODE

RT

R5

162k

BOOST2

SW2

BOOST1

SW1

L2

1µH

L1

0.68µH

0.1µF

V

OUT1

OUT2

3.3V AT 3A

1.8V AT 3A

V

ON1

ON2

FB2

V

FB1

SGND PGND

R4

54.9k

R2

24.3k

R3

12.1k

R1

12.1k

C

OUT1

47µF

OUT2

22µF

3633 TA05

3633fb

24

LTC3633

Typical applicaTions

1.2V/1.8V Buck Regulator with Coincident Tracking and 6V Input UVLO

V

IN

3.6V TO 15V

R7

154k

C1

47µF

×2

V

IN1

IN2

RUN1

RUN2

INTV

CC

ITH1

ITH2

C2

2.2µF

R8

40k

MODE/SYNC

V2P5

PHMODE

LTC3633

RT

TRACKSS2

R5

162k

BOOST2

SW2

BOOST1

SW1

L2

L1

0.68µH

0.1µF

0.47µH

V

OUT2

1.2V AT 3A

OUT1

1.8V AT 3A

V

ON1

ON2

V

FB1

FB2

SGND PGND

R4

10k

R6

4.99k

R2

15k

R3

10k

R1

10k

C

OUT2

68µF

C

OUT1

47µF

3633 TA03

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package

28-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663 Rev I)

Exposed Pad Variation EB

9.60 – 9.80*

(.378 – .386)

4.75

(.187)

4.75

(.187)

28 27 26 2524 23 22 21 20 1918 17 16 15

2.74

(.108)

EXPOSED

PAD HEAT SINK

ON BOTTOM OF

PACKAGE

6.60 ±0.10

4.50 ±0.10

SEE NOTE 4

6.40

(.252)

BSC

2.74

(.108)

0.45 ±0.05

1.05 ±0.10

0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT

5

7

1

2

3

4

6

8

9

10 12 13 14

11

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

FE28 (EB) TSSOP REV I 0211

0.195 – 0.30

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

MILLIMETERS

(INCHES)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3. DRAWING NOT TO SCALE

3633fb

25

LTC3633

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UFD Package

28-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1712 Rev B)

0.70 ±0.05

4.50 ± 0.05

3.10 ± 0.05

2.50 REF

2.65 ± 0.05

3.65 ± 0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

3.50 REF

4.10 ± 0.05

5.50 ± 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.20 OR 0.35

× 45° CHAMFER

2.50 REF

R = 0.115

TYP

R = 0.05

TYP

0.75 ± 0.05

4.00 ± 0.10

(2 SIDES)

27

28

0.40 ± 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 ± 0.10

(2 SIDES)

3.50 REF

3.65 ± 0.10

2.65 ± 0.10

(UFD28) QFN 0506 REV B

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3633fb

26

LTC3633

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

11/11 Updated Typical Application and Graph.

Updated Absolute Maximum Ratings section.

Updated • statement and Note 3 on Electrical Characteristics section.

Updated graphs G04, G05, G10 in Typical Performance Characteristics section.

Updated Block Diagram.

1

2

3, 4

5, 6

10

28

2

Updated Typical Application.

B

6/12

Clarified Absolute Maximum Ratings

Clarified Parametric Table

Clarified Pin Functions

3, 4

8, 9

10

Clarified Block Diagram

3633fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC3633

Typical applicaTion

3.3V/1.8V Buck Regulator with 2.5V LDO Output

V

IN

12V

C1

47µF

×2

V

IN1

IN2

RUN1

RUN2

INTV

CC

ITH1

ITH2

C2

2.2µF

PHMODE

MODE/SYNC

LTC3633

2.5V AT 10mA

1µF

RT

V2P5

R5

162k

BOOST2

SW2

BOOST1

SW1

L2

L1

1µH

0.1µF

0.68µH

V

OUT1

OUT2

1.8V AT 3A

3.3V AT 3A

V

ON1

ON2

FB2

V

FB1

SGND PGND

R4

20k

R2

R3

10k

R1

10k

C

OUT1

22µF

OUT2

45.3k

47µF

3633 TA04

relaTeD parTs

PART

DESCRIPTION

NUMBER

COMMENTS

LTC3605

LTC3603

LTC3602

LTC3601

15V, 5A (I ), 4MHz, Synchronous Step-Down DC/

95% Efficiency, V : 4V to 15V, V

= 0.6V, I = 2mA, I < 15µA,

OUT(MIN) Q SD

OUT

DC Converter

IN

4mm × 4mm QFN-24

15V, 2.5A (I ), 3MHz, Synchronous Step-Down DC/ 95% Efficiency, V : 4.5V to 15V, V

= 0.6V, I = 75µA, I < 1µA,

Q SD

OUT

IN

OUT(MIN)

DC Converter

4mm × 4mm QFN-20, MSOP-16E

10V, 2.5A (I ), 3MHz, Synchronous Step-Down DC/ 95% Efficiency, V : 4.5V to 10V, V

= 0.6V, I = 75µA, I < 1µA,

Q SD

OUT

IN

DC Converter

3mm × 3mm QFN-16, MSOP-16E

15V, 1.5A (I ), 4MHz, Synchronous Step-Down DC/ 95% Efficiency, V : 4.5V to 15V, V

= 0.6V, I = 300µA, I < 1µA,

Q SD

OUT

IN

DC Converter

4mm × 4mm QFN-20, MSOP-16E

3633fb

LT 0612 REV B • PRINTED IN USA

28 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

 LINEAR TECHNOLOGY CORPORATION 2010

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3601
厂家：	Linear Systems
描述：	Dual Channel 3A, 15V Monolithic Synchronous Step-Down Regulator 双通道3A， 15V单片同步降压型稳压器稳压器
文件：	总28页 (文件大小：404K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3601 [Linear Systems]

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